/*
 * Copyright     :  Copyright (C) 2022, Huawei Technologies Co. Ltd.
 * File name     :  stars_topic_sche_s_cfg_reg_offset.h
 * Project line  :  Platform And Key Technologies Development
 * Department    :  CAD Development Department
 * Author        :  xxx
 * Version       :  1
 * Date          :  2020/04/01
 * Description   :  The description of xxx project
 * Others        :  Generated automatically by nManager V5.1 
 * History       :  xxx 2022/03/16 11:06:47 Create file
 */

#ifndef __STARS_TOPIC_SCHE_S_CFG_REG_OFFSET_H__
#define __STARS_TOPIC_SCHE_S_CFG_REG_OFFSET_H__

/* STARS_TOPIC_SCHE_S_CFG Base address of Module's Register */
#define STARS_TOPIC_SCHE_S_CFG_BASE                       (0x4800000)

/******************************************************************************/
/*                      SOC STARS_TOPIC_SCHE_S_CFG Registers' Definitions                            */
/******************************************************************************/

#define STARS_TOPIC_SCHE_S_CFG_STARS_POOL_SEC_REG                               (STARS_TOPIC_SCHE_S_CFG_BASE + 0x0)    
#define STARS_TOPIC_SCHE_S_CFG_STARS_TOPIC_DEVICE_MB_AWCACHE_SETTING_REG        (STARS_TOPIC_SCHE_S_CFG_BASE + 0x800)  
#define STARS_TOPIC_SCHE_S_CFG_STARS_TOPIC_DEVICE_MB_S_AWPROT_SETTING_REG       (STARS_TOPIC_SCHE_S_CFG_BASE + 0x804)  
#define STARS_TOPIC_SCHE_S_CFG_STARS_TOPIC_DEVICE_MB_NS_AWPROT_SETTING_REG      (STARS_TOPIC_SCHE_S_CFG_BASE + 0x808)  
#define STARS_TOPIC_SCHE_S_CFG_STARS_TOPIC_HOST_MB_AWCACHE_SETTING_REG          (STARS_TOPIC_SCHE_S_CFG_BASE + 0x810)  
#define STARS_TOPIC_SCHE_S_CFG_STARS_TOPIC_HOST_MB_S_AWPROT_SETTING_REG         (STARS_TOPIC_SCHE_S_CFG_BASE + 0x814)  
#define STARS_TOPIC_SCHE_S_CFG_STARS_TOPIC_HOST_MB_NS_AWPROT_SETTING_REG        (STARS_TOPIC_SCHE_S_CFG_BASE + 0x818)  
#define STARS_TOPIC_SCHE_S_CFG_STARS_TOPIC_ARCACHE_SETTING_REG                  (STARS_TOPIC_SCHE_S_CFG_BASE + 0x820)  
#define STARS_TOPIC_SCHE_S_CFG_STARS_TOPIC_S_ARPROT_SETTING_REG                 (STARS_TOPIC_SCHE_S_CFG_BASE + 0x824)  
#define STARS_TOPIC_SCHE_S_CFG_STARS_TOPIC_NS_ARPROT_SETTING_REG                (STARS_TOPIC_SCHE_S_CFG_BASE + 0x828)  
#define STARS_TOPIC_SCHE_S_CFG_STARS_TOPIC_AICPU_POOL_FLAG_REG                  (STARS_TOPIC_SCHE_S_CFG_BASE + 0x830)  
#define STARS_TOPIC_SCHE_S_CFG_STARS_TOPIC_DEVICE_POOL_ENABLE_CTRL_S_0_REG      (STARS_TOPIC_SCHE_S_CFG_BASE + 0x840)  
#define STARS_TOPIC_SCHE_S_CFG_STARS_TOPIC_DEVICE_POOL_ENABLE_CTRL_S_1_REG      (STARS_TOPIC_SCHE_S_CFG_BASE + 0x844)  
#define STARS_TOPIC_SCHE_S_CFG_STARS_TOPIC_DEVICE_POOL_ENABLE_CTRL_S_2_REG      (STARS_TOPIC_SCHE_S_CFG_BASE + 0x848)  
#define STARS_TOPIC_SCHE_S_CFG_STARS_TOPIC_DEVICE_POOL_DISABLE_CTRL_S_0_REG     (STARS_TOPIC_SCHE_S_CFG_BASE + 0x880)  
#define STARS_TOPIC_SCHE_S_CFG_STARS_TOPIC_DEVICE_POOL_DISABLE_CTRL_S_1_REG     (STARS_TOPIC_SCHE_S_CFG_BASE + 0x884)  
#define STARS_TOPIC_SCHE_S_CFG_STARS_TOPIC_DEVICE_POOL_DISABLE_CTRL_S_2_REG     (STARS_TOPIC_SCHE_S_CFG_BASE + 0x888)  
#define STARS_TOPIC_SCHE_S_CFG_STARS_TOPIC_DEVICE_POOL0_STATUS_S_REG            (STARS_TOPIC_SCHE_S_CFG_BASE + 0x8C0)  
#define STARS_TOPIC_SCHE_S_CFG_STARS_TOPIC_DEVICE_POOL1_STATUS_S_REG            (STARS_TOPIC_SCHE_S_CFG_BASE + 0x8C4)  
#define STARS_TOPIC_SCHE_S_CFG_STARS_TOPIC_DEVICE_POOL2_STATUS_S_REG            (STARS_TOPIC_SCHE_S_CFG_BASE + 0x8C8)  
#define STARS_TOPIC_SCHE_S_CFG_STARS_TOPIC_DEVICE_CPU_STATUS_REPORT_S_0_REG     (STARS_TOPIC_SCHE_S_CFG_BASE + 0x2000) 
#define STARS_TOPIC_SCHE_S_CFG_STARS_TOPIC_DEVICE_CPU_STATUS_REPORT_S_1_REG     (STARS_TOPIC_SCHE_S_CFG_BASE + 0x2020) 
#define STARS_TOPIC_SCHE_S_CFG_STARS_TOPIC_DEVICE_CPU_STATUS_REPORT_S_2_REG     (STARS_TOPIC_SCHE_S_CFG_BASE + 0x2040) 
#define STARS_TOPIC_SCHE_S_CFG_STARS_TOPIC_DEVICE_CPU_STATUS_REPORT_S_3_REG     (STARS_TOPIC_SCHE_S_CFG_BASE + 0x2060) 
#define STARS_TOPIC_SCHE_S_CFG_STARS_TOPIC_DEVICE_CPU_STATUS_REPORT_S_4_REG     (STARS_TOPIC_SCHE_S_CFG_BASE + 0x2080) 
#define STARS_TOPIC_SCHE_S_CFG_STARS_TOPIC_DEVICE_CPU_STATUS_REPORT_S_5_REG     (STARS_TOPIC_SCHE_S_CFG_BASE + 0x20A0) 
#define STARS_TOPIC_SCHE_S_CFG_STARS_TOPIC_DEVICE_CPU_STATUS_REPORT_S_6_REG     (STARS_TOPIC_SCHE_S_CFG_BASE + 0x20C0) 
#define STARS_TOPIC_SCHE_S_CFG_STARS_TOPIC_DEVICE_CPU_STATUS_REPORT_S_7_REG     (STARS_TOPIC_SCHE_S_CFG_BASE + 0x20E0) 
#define STARS_TOPIC_SCHE_S_CFG_STARS_TOPIC_DEVICE_CPU_WAIT_TOPIC_S_0_REG        (STARS_TOPIC_SCHE_S_CFG_BASE + 0x2004) 
#define STARS_TOPIC_SCHE_S_CFG_STARS_TOPIC_DEVICE_CPU_WAIT_TOPIC_S_1_REG        (STARS_TOPIC_SCHE_S_CFG_BASE + 0x2024) 
#define STARS_TOPIC_SCHE_S_CFG_STARS_TOPIC_DEVICE_CPU_WAIT_TOPIC_S_2_REG        (STARS_TOPIC_SCHE_S_CFG_BASE + 0x2044) 
#define STARS_TOPIC_SCHE_S_CFG_STARS_TOPIC_DEVICE_CPU_WAIT_TOPIC_S_3_REG        (STARS_TOPIC_SCHE_S_CFG_BASE + 0x2064) 
#define STARS_TOPIC_SCHE_S_CFG_STARS_TOPIC_DEVICE_CPU_WAIT_TOPIC_S_4_REG        (STARS_TOPIC_SCHE_S_CFG_BASE + 0x2084) 
#define STARS_TOPIC_SCHE_S_CFG_STARS_TOPIC_DEVICE_CPU_WAIT_TOPIC_S_5_REG        (STARS_TOPIC_SCHE_S_CFG_BASE + 0x20A4) 
#define STARS_TOPIC_SCHE_S_CFG_STARS_TOPIC_DEVICE_CPU_WAIT_TOPIC_S_6_REG        (STARS_TOPIC_SCHE_S_CFG_BASE + 0x20C4) 
#define STARS_TOPIC_SCHE_S_CFG_STARS_TOPIC_DEVICE_CPU_WAIT_TOPIC_S_7_REG        (STARS_TOPIC_SCHE_S_CFG_BASE + 0x20E4) 
#define STARS_TOPIC_SCHE_S_CFG_STARS_TOPIC_DEVICE_CPU_INT_EN_S_0_REG            (STARS_TOPIC_SCHE_S_CFG_BASE + 0x2008) 
#define STARS_TOPIC_SCHE_S_CFG_STARS_TOPIC_DEVICE_CPU_INT_EN_S_1_REG            (STARS_TOPIC_SCHE_S_CFG_BASE + 0x2028) 
#define STARS_TOPIC_SCHE_S_CFG_STARS_TOPIC_DEVICE_CPU_INT_EN_S_2_REG            (STARS_TOPIC_SCHE_S_CFG_BASE + 0x2048) 
#define STARS_TOPIC_SCHE_S_CFG_STARS_TOPIC_DEVICE_CPU_INT_EN_S_3_REG            (STARS_TOPIC_SCHE_S_CFG_BASE + 0x2068) 
#define STARS_TOPIC_SCHE_S_CFG_STARS_TOPIC_DEVICE_CPU_INT_EN_S_4_REG            (STARS_TOPIC_SCHE_S_CFG_BASE + 0x2088) 
#define STARS_TOPIC_SCHE_S_CFG_STARS_TOPIC_DEVICE_CPU_INT_EN_S_5_REG            (STARS_TOPIC_SCHE_S_CFG_BASE + 0x20A8) 
#define STARS_TOPIC_SCHE_S_CFG_STARS_TOPIC_DEVICE_CPU_INT_EN_S_6_REG            (STARS_TOPIC_SCHE_S_CFG_BASE + 0x20C8) 
#define STARS_TOPIC_SCHE_S_CFG_STARS_TOPIC_DEVICE_CPU_INT_EN_S_7_REG            (STARS_TOPIC_SCHE_S_CFG_BASE + 0x20E8) 
#define STARS_TOPIC_SCHE_S_CFG_STARS_TOPIC_DEVICE_CPU_ERROR_CODE_S_0_REG        (STARS_TOPIC_SCHE_S_CFG_BASE + 0x200C) 
#define STARS_TOPIC_SCHE_S_CFG_STARS_TOPIC_DEVICE_CPU_ERROR_CODE_S_1_REG        (STARS_TOPIC_SCHE_S_CFG_BASE + 0x202C) 
#define STARS_TOPIC_SCHE_S_CFG_STARS_TOPIC_DEVICE_CPU_ERROR_CODE_S_2_REG        (STARS_TOPIC_SCHE_S_CFG_BASE + 0x204C) 
#define STARS_TOPIC_SCHE_S_CFG_STARS_TOPIC_DEVICE_CPU_ERROR_CODE_S_3_REG        (STARS_TOPIC_SCHE_S_CFG_BASE + 0x206C) 
#define STARS_TOPIC_SCHE_S_CFG_STARS_TOPIC_DEVICE_CPU_ERROR_CODE_S_4_REG        (STARS_TOPIC_SCHE_S_CFG_BASE + 0x208C) 
#define STARS_TOPIC_SCHE_S_CFG_STARS_TOPIC_DEVICE_CPU_ERROR_CODE_S_5_REG        (STARS_TOPIC_SCHE_S_CFG_BASE + 0x20AC) 
#define STARS_TOPIC_SCHE_S_CFG_STARS_TOPIC_DEVICE_CPU_ERROR_CODE_S_6_REG        (STARS_TOPIC_SCHE_S_CFG_BASE + 0x20CC) 
#define STARS_TOPIC_SCHE_S_CFG_STARS_TOPIC_DEVICE_CPU_ERROR_CODE_S_7_REG        (STARS_TOPIC_SCHE_S_CFG_BASE + 0x20EC) 
#define STARS_TOPIC_SCHE_S_CFG_STARS_TOPIC_DEVICE_CPU_GET_STATUS_REPORT_S_0_REG (STARS_TOPIC_SCHE_S_CFG_BASE + 0x2010) 
#define STARS_TOPIC_SCHE_S_CFG_STARS_TOPIC_DEVICE_CPU_GET_STATUS_REPORT_S_1_REG (STARS_TOPIC_SCHE_S_CFG_BASE + 0x2030) 
#define STARS_TOPIC_SCHE_S_CFG_STARS_TOPIC_DEVICE_CPU_GET_STATUS_REPORT_S_2_REG (STARS_TOPIC_SCHE_S_CFG_BASE + 0x2050) 
#define STARS_TOPIC_SCHE_S_CFG_STARS_TOPIC_DEVICE_CPU_GET_STATUS_REPORT_S_3_REG (STARS_TOPIC_SCHE_S_CFG_BASE + 0x2070) 
#define STARS_TOPIC_SCHE_S_CFG_STARS_TOPIC_DEVICE_CPU_GET_STATUS_REPORT_S_4_REG (STARS_TOPIC_SCHE_S_CFG_BASE + 0x2090) 
#define STARS_TOPIC_SCHE_S_CFG_STARS_TOPIC_DEVICE_CPU_GET_STATUS_REPORT_S_5_REG (STARS_TOPIC_SCHE_S_CFG_BASE + 0x20B0) 
#define STARS_TOPIC_SCHE_S_CFG_STARS_TOPIC_DEVICE_CPU_GET_STATUS_REPORT_S_6_REG (STARS_TOPIC_SCHE_S_CFG_BASE + 0x20D0) 
#define STARS_TOPIC_SCHE_S_CFG_STARS_TOPIC_DEVICE_CPU_GET_STATUS_REPORT_S_7_REG (STARS_TOPIC_SCHE_S_CFG_BASE + 0x20F0) 
#define STARS_TOPIC_SCHE_S_CFG_STARS_TOPIC_DEVICE_CPU_GET_TOPIC_S_0_REG         (STARS_TOPIC_SCHE_S_CFG_BASE + 0x2014) 
#define STARS_TOPIC_SCHE_S_CFG_STARS_TOPIC_DEVICE_CPU_GET_TOPIC_S_1_REG         (STARS_TOPIC_SCHE_S_CFG_BASE + 0x2034) 
#define STARS_TOPIC_SCHE_S_CFG_STARS_TOPIC_DEVICE_CPU_GET_TOPIC_S_2_REG         (STARS_TOPIC_SCHE_S_CFG_BASE + 0x2054) 
#define STARS_TOPIC_SCHE_S_CFG_STARS_TOPIC_DEVICE_CPU_GET_TOPIC_S_3_REG         (STARS_TOPIC_SCHE_S_CFG_BASE + 0x2074) 
#define STARS_TOPIC_SCHE_S_CFG_STARS_TOPIC_DEVICE_CPU_GET_TOPIC_S_4_REG         (STARS_TOPIC_SCHE_S_CFG_BASE + 0x2094) 
#define STARS_TOPIC_SCHE_S_CFG_STARS_TOPIC_DEVICE_CPU_GET_TOPIC_S_5_REG         (STARS_TOPIC_SCHE_S_CFG_BASE + 0x20B4) 
#define STARS_TOPIC_SCHE_S_CFG_STARS_TOPIC_DEVICE_CPU_GET_TOPIC_S_6_REG         (STARS_TOPIC_SCHE_S_CFG_BASE + 0x20D4) 
#define STARS_TOPIC_SCHE_S_CFG_STARS_TOPIC_DEVICE_CPU_GET_TOPIC_S_7_REG         (STARS_TOPIC_SCHE_S_CFG_BASE + 0x20F4) 
#define STARS_TOPIC_SCHE_S_CFG_STARS_TOPIC_STARS_CPU_STATUS_REPORT_S_0_REG      (STARS_TOPIC_SCHE_S_CFG_BASE + 0x2200) 
#define STARS_TOPIC_SCHE_S_CFG_STARS_TOPIC_STARS_CPU_STATUS_REPORT_S_1_REG      (STARS_TOPIC_SCHE_S_CFG_BASE + 0x2220) 
#define STARS_TOPIC_SCHE_S_CFG_STARS_TOPIC_STARS_CPU_WAIT_TOPIC_S_0_REG         (STARS_TOPIC_SCHE_S_CFG_BASE + 0x2204) 
#define STARS_TOPIC_SCHE_S_CFG_STARS_TOPIC_STARS_CPU_WAIT_TOPIC_S_1_REG         (STARS_TOPIC_SCHE_S_CFG_BASE + 0x2224) 
#define STARS_TOPIC_SCHE_S_CFG_STARS_TOPIC_STARS_CPU_INT_EN_S_0_REG             (STARS_TOPIC_SCHE_S_CFG_BASE + 0x2208) 
#define STARS_TOPIC_SCHE_S_CFG_STARS_TOPIC_STARS_CPU_INT_EN_S_1_REG             (STARS_TOPIC_SCHE_S_CFG_BASE + 0x2228) 
#define STARS_TOPIC_SCHE_S_CFG_STARS_TOPIC_STARS_CPU_ERROR_CODE_S_0_REG         (STARS_TOPIC_SCHE_S_CFG_BASE + 0x220C) 
#define STARS_TOPIC_SCHE_S_CFG_STARS_TOPIC_STARS_CPU_ERROR_CODE_S_1_REG         (STARS_TOPIC_SCHE_S_CFG_BASE + 0x222C) 
#define STARS_TOPIC_SCHE_S_CFG_STARS_TOPIC_POOL_QUEUE_SCH_S_0_REG               (STARS_TOPIC_SCHE_S_CFG_BASE + 0x2300) 
#define STARS_TOPIC_SCHE_S_CFG_STARS_TOPIC_POOL_QUEUE_SCH_S_1_REG               (STARS_TOPIC_SCHE_S_CFG_BASE + 0x2304) 
#define STARS_TOPIC_SCHE_S_CFG_STARS_TOPIC_POOL_QUEUE_SCH_S_2_REG               (STARS_TOPIC_SCHE_S_CFG_BASE + 0x2308) 
#define STARS_TOPIC_SCHE_S_CFG_STARS_TOPIC_POOL_WRR_WEIGHT0_S_0_REG             (STARS_TOPIC_SCHE_S_CFG_BASE + 0x2320) 
#define STARS_TOPIC_SCHE_S_CFG_STARS_TOPIC_POOL_WRR_WEIGHT0_S_1_REG             (STARS_TOPIC_SCHE_S_CFG_BASE + 0x2324) 
#define STARS_TOPIC_SCHE_S_CFG_STARS_TOPIC_POOL_WRR_WEIGHT0_S_2_REG             (STARS_TOPIC_SCHE_S_CFG_BASE + 0x2328) 
#define STARS_TOPIC_SCHE_S_CFG_STARS_TOPIC_POOL_WRR_WEIGHT1_S_0_REG             (STARS_TOPIC_SCHE_S_CFG_BASE + 0x2340) 
#define STARS_TOPIC_SCHE_S_CFG_STARS_TOPIC_POOL_WRR_WEIGHT1_S_1_REG             (STARS_TOPIC_SCHE_S_CFG_BASE + 0x2344) 
#define STARS_TOPIC_SCHE_S_CFG_STARS_TOPIC_POOL_WRR_WEIGHT1_S_2_REG             (STARS_TOPIC_SCHE_S_CFG_BASE + 0x2348) 
#define STARS_TOPIC_SCHE_S_CFG_STARS_TOPIC_DEVICE_CPU_INT_STS_S_REG             (STARS_TOPIC_SCHE_S_CFG_BASE + 0x4000) 
#define STARS_TOPIC_SCHE_S_CFG_STARS_TOPIC_DEVICE_CPU_INT_FORCE_S_REG           (STARS_TOPIC_SCHE_S_CFG_BASE + 0x4004) 
#define STARS_TOPIC_SCHE_S_CFG_STARS_TOPIC_DEVICE_CPU_INT_CLR_S_REG             (STARS_TOPIC_SCHE_S_CFG_BASE + 0x4008) 
#define STARS_TOPIC_SCHE_S_CFG_STARS_TOPIC_DEVICE_CPU_INT_MASK_S_REG            (STARS_TOPIC_SCHE_S_CFG_BASE + 0x400C) 
#define STARS_TOPIC_SCHE_S_CFG_STARS_TOPIC_DEVICE_CPU_INT_RAW_S_REG             (STARS_TOPIC_SCHE_S_CFG_BASE + 0x4010) 

#endif // __STARS_TOPIC_SCHE_S_CFG_REG_OFFSET_H__
